1. Field of the Invention
The present invention generally relates to a circuit board, and more particularly, to a chip package carrier and a fabrication method thereof.
2. Description of Related Art
Along with the progress of the semiconductor technology, a chip nowadays employs a lot of transistors disposed therein and arranged in high density, and a lot of pads are disposed on a surface of the chip, wherein the chip is usually mounted on a chip package carrier and then packaged to form a chip package. The chip package carrier today usually has embedded capacitor devices, so that a chip package carrier with the embedded capacitor devices can reduce the amount of surface mounted capacitor device disposed thereon.
FIG. 1 is a sectional diagram of a conventional chip package carrier with a chip mounted thereon. Referring to FIG. 1, a conventional chip package carrier 100 includes two copper circuit layers 110a and 110b, two dielectric layers 120a and 120b, two solder mask layers 130a and 130b, a via plug 140 and an embedded capacitor device 150, wherein the chip package carrier 100 is electrically connected to a chip 10 through a plurality of solder bumps S1.
The embedded capacitor device 150 is disposed between the dielectric layers 120a and 120b, and the dielectric layers 120a and 120b respectively cover both the opposite surfaces of the embedded capacitor device 150. The copper circuit layers 110a and 110b are respectively located on the dielectric layers 120a and 120b, and the via plug 140 is connected between the copper circuit layers 110a and 110b. 
The copper circuit layer 110a includes a plurality of traces 112a and a plurality of pads 114a, and the copper circuit layer 110b includes a plurality of traces 112b. The solder mask layer 130a covers the traces 112a and makes the pads 114a exposed; the solder mask layer 130b covers the traces 112b. The solder bumps S1 are connected between the pads 114a and the chip 10 so that the chip 10 is electrically connected to the chip package carrier 100.
The embedded capacitor device 150 includes an upper electrode 152a, a lower electrode 152b and a ceramic dielectric layer 154, wherein the upper electrode 152a does not contact the lower electrode 152b, and the ceramic dielectric layer 154 is disposed between the upper electrode 152a and the lower electrode 152b. In addition, the chip package carrier 100 further includes a pair of via plugs 160a and 160b, wherein the via plug 160a is connected between one of the pads 114a and the upper electrode 152a, and the via plug 160b is connected between another of the pads 114a and the lower electrode 152b, so that the chip is electrically connected to the embedded capacitor device 150.
The shorter distance D1 between the chip 10 and the embedded capacitor device 150, the less noise interference on the chip package carrier is, which is particularly obvious and important in a high-frequency signal propagation. Since the embedded capacitor device 150 usually has a low alignment accuracy, the embedded capacitor device 150 must take a wiring route through the via plugs 160a and 160b and the solder bumps S1 to connect the chip 10. However, when the number of the embedded capacitor devices 150 is too large, the horizontal disposition space of the conventional chip package carrier 100 is not sufficient to dispose the embedded capacitor devices 150 in horizontal disposition mode. On the other hand, to solve the above-mentioned problem, the size of the chip package carrier 100 must be increased, which makes the dimensions of a conventional chip package from being shortened. In this regard, many relevant companies have made great efforts and expect a solution to shorten the horizontal disposition space of the embedded capacitor device 150 and increase the signal transmission quality of the chip package carrier 100.